1. Field of the Invention
The present invention relates to a method for verification of hardware design, and particularly to a method for random functional verification of hardware design that supports hardware simulation of branch and interrupt instructions.
2. Description of the Related Art
In a process of developing semiconductor integrated circuits such as a large scale integrated circuit (LSI), a design method using a computer aided design (CAD) tool is employed. Such a design environment using a CAD tool is also referred to an electronic design automation (EDA) environment. In such a semiconductor development process incorporating the CAD tool, desired semiconductor circuits are created in an LSI with the use of a hardware description language such as VHDL and Verilog.
After the design stage of the LSI circuit, actual LSI devices are taped out and the LSI product is tested by a semiconductor test system such as an LSI tester to determine whether the LSI devices perform the intended functions properly. An LSI tester supplies a test pattern to an LSI device under test and compares the resultant outputs of the LSI device with expected data to determine pass or fail of the LSI device. For testing an LSI device with higher level functionality and density, a test pattern to be applied to the LSI device must accordingly be complex and lengthy, resulting in significantly large work load and work hours in procuring the test pattern. Therefore, it is not preferable to produce a test pattern when an LSI device under test is actually produced, especially for LSI devices of shorter life cycles, because it causes delayed time to market.
Thus, to improve overall test efficiency and productivity of the semiconductor integrated circuits, it is a common practice to make use of the data produced through the operation of a software simulator in an actual test of the semiconductor integrated circuits. The software simulator evaluates the functionality of the semiconductor circuits. To verify a design, one needs to: write executable test scenarios that include expected results, simulate these test scenarios against a software or a hardware design model, compare the expected results with the actual results obtained from the simulation, and evaluate the appropriateness and quality of the test scenarios.
Random testing and the microprocessor variant called random code generation have been used extensively to exercise and verify the correctness of complex designs. A key aspect of all random testing is to use a pseudo-random number generator to assist in creating stimulus to exercise the design. The usefulness of a random test generator is directly related to the quality of test cases produced.
Conventional random code generation designs have used rules to constrain the amount of randomness used in the testing to avoid illegal cases and focus the cases on interesting aspects of the design. Purely random testing produces too many illegal cases and does not stress complex designs thoroughly enough to be of real value. For example, the branch and interrupt are difficult to deal with since the branch offset is random and the gap between the branch instruction and its target should be filled with instructions which are never executed, and asynchronous nature of interrupts, it is vital to ensure the correct prioritization of interrupt messages over normal messages, i.e. identified program part.